Apparatuses consistent with exemplary embodiments relate to an application processor, and more particularly, to an application processor including a scheduler which checks the status of a core, a system on chip (SoC) including the scheduler which checks the status of the core, and a computing apparatus including the SoC.
Recently, microprocessors may include a plurality of cores. In particular, an application processor used in a mobile computing apparatus having limited power supply uses heterogeneous multi-processor (HMP) architecture to be flexible in responding to requirements of high performance and low power. The HMP architecture controls the level of an operating voltage of a core and/or the frequency of a clock signal for the core to reduce power consumption during the idle time of the core.
In the HMP architecture including a low-performance low-power core and a high-performance high-power core, the high-performance high-power core is shut off from the operating voltage and the clock signal most of the time. When a task which has been executed in the low-performance low-power core is migrated to the high-performance high-power core due to an increase in a workload of the task, a scheduler which migrates the task cannot check the status of the high-performance high-power core, and therefore, the task falls into a standby mode until the high-performance high-power core, which has been shut off from the operating voltage and the clock signal, becomes operable. As a result, the performance is deteriorated.